DS400 Datasheet, PDF (1/45 Pages) Xilinx, Inc – PLB address pipelining

DS400 April 24, 2009
0
Processor Local Bus (PLB) v3.4
(v1.02a)
0 0 _{Product Specification}
Introduction
The Xilinx 64-bit Processor Local Bus (PLB) consists of a
bus control unit, a watchdog timer, and separate address,
write, and read data path units with a a three-cycle only
arbitration feature. It contains a DCR slave interface to pro-
vide access to its bus error status registers. It also contains
a power-up reset circuit to ensure a PLB reset is generated
if no external reset has been provided. The IBM Processor
Local Bus (PLB) 64-Bit Architecture Specification and the
IBM Processor Local Bus (PLB) 64-Bit Arbiter Core User
Manual are referenced throughout this document. Differ-
ences between IBM PLB Arbiter and Xilinx PLB are high-
lighted and explained in Specification Exceptions.
Features
• PLB arbitration support for up to 16 masters
- Number of PLB masters is configurable via a
design parameter
• PLB address and data steering support for up to 16
masters
• 64-bit and/or 32-bit support for masters and slaves
• PLB address pipelining
• Three-cycle arbitration
• Four levels of dynamic master request priority
• PLB watchdog timer
• PLB architecture compliant
• Complete PLB Bus structure provided
- Up to 16 slaves supported; configurable via a
design parameter
- No external or gates required for PLB slave input
signals
• PLB Reset circuit
- PLB Reset generated synchronously to the PLB
clock upon power up if no external reset is provided
- PLB Reset generated synchronously from external
reset when external reset provided
- Active state of external reset selectable via a
design parameter
LogiCORE™ IP Facts
Core Specifics
See EDK Supported Device Families.
Version of core
plb_v34
v1.02a
Resources Used
Min
Max
Slice
223
1645
LUTs
270
2540
FFs
59
484
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation
N/A
Template
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
Verification
See Tools for requirements.
Simulation
Synthesis
Support
Support provided by Xilinx, Inc.
• System compatibility with the Xilinx OPB Master/Slave
IPIF architecture when utilized with PLB2OPB bridge
core version 1.01.a.
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countries. All other trademarks are the property of their respective owners.
DS400 April 24, 2009
www.xilinx.com
1
Product Specification
1-800-255-7778