DS318 Datasheet, PDF (1/19 Pages) Xilinx, Inc – 3GPP Turbo Decoder v4.0

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3GPP Turbo Decoder v4.0
DS318 June 24, 2009
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Product Specification
Introduction
General Description
The Turbo Convolution Code (TCC) Decoder core is
used in conjunction with a TCC Encoder to provide an
extremely effective way of transmitting data reliably
over noisy data channels, and is designed to meet the
D_{3GPP Mobile Communication System specification.}
Features
i_{• Drop-in module for Virtex™-4, Virtex-5, Virtex-6,}
s _{Spartan™-3, Spartan-3E, Spartan-3A/3AN/3A DSP,}
Spartan 6 FPGAs
c _{• Implements the 3GPP/UMTS specification [1]}
• Core contains the full 3GPP interleaver
o _{• Full 3GPP block size range supported, that is,}
40 - 5114
n _{• Dynamically selectable number of iterations 1-15}
• Number representation: two’s complement
t _{fractional numbers:}
i _{- Data input: 2 or 3 integer bits and 1 to 4 fractional}
n _bits
- Internal calculations: 6 or 7 integer bits and 1 to 4
u _{fractional bits}
• Fast Termination option
e _{• Support for rate 1/3 or rate 1/5 coded input}
• Available through the Xilinx CORE Generator™
d _{11.2 and later}
Applications
I The TCC Decoder core is designed to meet the 3GPP
P ^{Mobile Communication System specification [1].}
The TCC Decoder is used in conjunction with a TCC
Encoder to provide an extremely effective way of trans-
mitting data reliably over noisy data channels. The
Turbo Decoder operates very well under low sig-
nal-to-noise conditions and provides a performance
close to the theoretical optimal performance defined by
the Shannon limit [2].
When a decode operation is started, the core accepts the
block size and the number of iterations from two input
ports. A block data load stage follows, in which the sys-
tematic and parity data is read into the core in parallel
on a clock-by-clock basis and stored in internal block
RAM. The core then starts the decoding process and
implements the required number of iterations. Decod-
ing may optionally be terminated earlier if the Fast Ter-
mination unit is included. Finally, the decoded bit
sequence is output. The entire sequence is automati-
cally controlled from a single first data signal and
requires no user intervention. All the interleaving oper-
ations required in the 3GPP specification are handled
automatically within the core.
The core expects two’s complement fractional numbers
as inputs and also uses this format for the internal cal-
culations. Each fractional input number represents the
Log Likelihood Ratio (LLR) divided by 2 for each input
bit. This LLR value can be considered to be the confi-
dence level that a particular bit is a one or zero. The
user can trade off accuracy against speed and complex-
ity by selecting the numerical precision that is required.
The input data can have two or three integer bits and
between one and four fractional bits. The precision of
the internal calculations can also be controlled using six
or seven integer bits and between one and four frac-
tional bits. (The number of input fractional bits must be
less than or equal to the number of internal calculation
fractional bits.)
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DS318 June 24, 2009
www.xilinx.com
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Product Specification