DS315 Datasheet, PDF (1/14 Pages) Xilinx, Inc – CoolRunner-II Automotive CPLD

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CoolRunner-II Automotive CPLD
Product Family
DS315 (v1.1) October 31, 2006
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Features
• AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
• Guaranteed to meet full electrical specifications over
T_A = -40° C to +105° C with T_J Maximum = +125° C
(Q-grade)
• Optimized for 1.8V systems
- Industry’s fastest low power CPLD
- Densities from 32 to 384 macrocells
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
- Guaranteed 1,000 program/erase cycles
- Guaranteed 20 year data retention
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Multiple I/O banks on all devices
- Unsurpassed low power management
· DataGATE external signal control
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Abundant product term clocks, output enables and
set/resets
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pullup on select
I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
- Hot pluggable
• PLA architecture
- Superior pinout retention
- 100% product term routability across function block
• Wide package availability including fine pitch:
- Chip Scale BGA, TQFP, and VQFP packages
- XA devices use Pb-free packages
• Design entry/verification using Xilinx and industry
standard CAE tools
• Free software support for all densities using Xilinx
WebPACK™
WARNING: Programming temperature range of
T_A = 0° C to +70° C
Family Overview
Xilinx CoolRunner™-II Automotive CPLDs deliver the high
speed and ease of use associated with the XA9500XL
CPLD family, along with extremely low power versatility in a
single CPLD. This means that the exact same parts can be
used for high-speed data communications/ computing sys-
tems and leading edge portable products, with the added
benefit of In System Programming. Low power consumption
and high-speed operation are combined into a single family
that is easy to use and cost effective. Clocking techniques
and other power saving features extend the users’ power
budget. The design features are supported with Xilinx ISE
WebPACK. Additional details can be found in Further
Reading, page 13.
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II Automotive CPLD family.
Table 1: CoolRunner-II Automotive CPLD Family Parameters
XA2C32A
XA2C64A
XA2C128
XA2C256
XA2C384
Macrocells
32
64
128
256
384
Max I/O
33
64
100
118
118
T_PD (ns)
5.5
6.7
7.0
7.0
9.2
T_SU (ns)
2.6
2.5
3.0
2.8
3.3
T_CO (ns)
4.7
6.0
5.4
6.0
7.9
F_SYSTEM1 (MHz)
200
159
152
152
125
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DS315 (v1.1) October 31, 2006
www.xilinx.com
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Product Specification