DS312_09 Datasheet, PDF (1/233 Pages) –

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Spartan-3E FPGA Family:
Data Sheet
DS312 (v3.8) August 26, 2009
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Module 1:
Spartan-3E FPGA Family: Introduction
and Ordering Information
DS312-1 (v3.8) August 26, 2009
• Introduction
• Features
• Architectural Overview
• Package Marking
• Ordering Information
Module 2:
Functional Description
DS312-2 (v3.8) August 26, 2009
• Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
• Powering Spartan®-3E FPGAs
• Production Stepping
Module 3:
DC and Switching Characteristics
DS312-3 (v3.8) August 26, 2009
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- I/O Timing
- SLICE Timing
- DCM Timing
- Block RAM Timing
- Multiplier Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v3.8) August 26, 2009
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
© 2005–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other coun-
tries. All other trademarks are the property of their respective owners.
DS312 (v3.8) August 26, 2009
www.xilinx.com
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