DS309 Datasheet, PDF (1/6 Pages) Xilinx, Inc – FCB to FSL Bridge

FCB to FSL Bridge (v1.00a)
DS309 April 24, 2009
Product Specification
Introduction
The FCB to FSL Bridge combines the power of the Virtex^®-4
PowerPC^® APU controller with the ease of use of the Fast
Simplex Link (FSL) protocol. The core connects FSL
interfaced co-processor cores to the PowerPC 405
processore via the Fabric Co-processor Bus (FCB). This
makes it easy to extend the PowerPC processing unit with
application specific functions. The FSL protocol is fully
compatible with the FSL ports on MicroBlaze™.
For more information on the APU Controller see the
PowerPC 405 Processor Block Reference Guide [Ref1].
For more information on the FSL protocol see Fast Simplex
Link [Ref2]
For more information on the FCB core see the Fabric
Co-processor Bus [Ref3].
Features
• Support for between 1 and 32 FSL master-slave pairs
• Support for all 8 FSL instructions:
- get: data read from slave FSL
- cget: control read from slave FSL
- nget: non-blocking data read from slave FSL
- ncget: non-blocking control read from slave FSL
- put: data write to master FSL
- cput: control write to master FSL
- nput: non-blocking data write to master FSL
- ncput: non-blocking control write to master FSL
• Support for both APU controller decoding using User
Defined Instructions (UDI), and Fabric Co-processor
Module (FCM) decoding
• FSL control error flagged as XEROV
• Failed non-blocking FSL access is flagged as XERCA
LogiCORE™ Facts
Core Specifics
Supported Device
Family
See EDK Supported Device
Families.
Version of Core
FCB2FSL_bridge
v1.00a
Resources Used
Min
Max
Slices
LUTs
FFs
N.A.
N.A.
31
145¹
48
89¹
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation
Template
N/A
Reference Designs
N/A
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
See Tools for requirements.
Synthesis
Support
Provided by Xilinx, Inc.
1.Assuming 3 FSL pairs. Size depends on number of
pairs enabled, and width of FSL data connected to the
core.
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tries. All other trademarks are the property of their respective owners.
DS309 April 24, 2009
www.xilinx.com
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Product Specification