DS308 Datasheet, PDF (1/8 Pages) Xilinx, Inc – Fabric Co-processor Bus

DS308 April 24, 2009
Fabric Co-processor Bus (FCB)
(v1.00a)
Product Specification
Introduction
The Fabric Co-processor Bus (FCB) connects one or
more FPGA fabric accelerator slaves to the Auxiliary
Processor Unit (APU) controller in a Virtex®-4
PowerPC® 405.
The slave access decoding is based on the APU instruc-
tion code. Each slave must decode a unique set of
instructions.
Features
• Single master support
• Multiple slave support
• Slave access selection based on instruction code
• No arbitration between slaves
• Implements the full Fabric Co-processor Module
(FCM) interface of the APU controller
• Developed for use with the FCB2FSL_bridge core,
and the PPC405_virtex4 wrapper
For more information on the PowerPC APU interface,
see [Ref 1].
LogiCORE™ IP Facts
Core Specifics
Supported Device
Family
Virtex^®-4
Version of Core
fcb_v10
v1.00a
Resources Used
Min
Max
Slices
LUTs
N/A
N/A
0
214 ⁽¹⁾
FFs
0
0
Block RAMs
0
0
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 11.1 or higher
Verification
N/A
Simulation
Mentor Graphics® ModelSim®
6.4b or later
Synthesis
XST
Support
Provided by Xilinx, Inc.
1. Assuming three full feature FCB slaves. Actual size depends on
number of slaves and the portion of the FCM interface signals they
use.
© 2004-2009 Xilinx, Inc., XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective
owners.
DS308 April 24, 2009
www.xilinx.com
1
Product Specification