DS306 Datasheet, PDF (1/12 Pages) Xilinx, Inc – Processor Local Bus (PLB) version 4.6 interfaces

DS306 April 24, 2009
Virtex-4 FPGA Embedded
Processor Block with PowerPC
405 Processor (v2.01b)
Product Specification
Introduction
This document describes the wrapper for the Virtex^®-4
FPGA embedded processor block. For details regarding
the Virtex-4 embedded block, see the Embedded
Processor Block in Virtex-4 FPGAs Reference Guide.
Features
• Processor Local Bus (PLB) version 4.6 interfaces
• Dual Instruction-side and dual data-side PLB
interfaces, with user-selectable address ranges and
clock frequency translation
• Instruction-side and data-side On-Chip Memory
(OCM) interfaces, with user-selectable address
ranges
• PowerPC^® 405 Auxiliary Processor Unit (APU)
controller interface, with User-Defined Instruction
decoding (UDI)
LogiCORE™ Facts
Core Specifics
Supported Device
Family
See EDK Supported Device
Families.
Version of Core
ppc405_virtex4
v2.01b
Resources Used
Min
Max
Slices
145
280
LUTs
125
420
FFs
225
390
Block RAMs
0
0
Special Features
PPC405_ADV
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Reference Designs
N/A
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
See Tools for requirements.
Synthesis
Support
Provided by Xilinx, Inc.
© 2008-2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All
other trademarks are the property of their respective owners.
DS306 April 24, 2009
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Product Specification