DS283 Datasheet, PDF (1/7 Pages) Xilinx, Inc – ChipScope PLB IBA

ChipScope PLB IBA
(Bus Analyzer) (v. 1.01a)
DS283 April 7, 2009
Product Specification
Introduction
The ChipScope™ PLB IBA core is a specialized Bus Ana-
lyzer core designed to debug embedded systems that contain
the IBM CoreConnect Processor Local Bus (PLB). The Chip-
Scope PLB IBA core in EDK is based on Tcl script that gen-
erates a HDL wrapper to the PLB IBA and calls the
ChipScope Core Generator to generate the netlist based on
user parameters.
Features
• Multiple Match Units for Trigger and Data capture
• Each Match Unit can be enabled and configured
independently
• The Match Units for the PLB IBA are:
− PLB Control signals
− PLB Address Units
− PLB Read Data Unit
− PLB Write Data Units
− PLB Master Units (based on no. of masters)
− PLB Slave Units (based on no. of slaves)
• Generic Trigger/Data Unit with selectable width
• For more information refer to the ChipScope Pro
Software and Cores User Guide in the ChipScope
installation
For more information about the PLB IBA core, refer to the
ChipScope Pro Software and Cores User Guide.
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex®-4
Version of Core
chipscope_plb_iba
v1.01a
Resources Used
Min
Max
Slices
219
411
LUTs
87
112
FFs
215
320
Block RAMs
1
187
Provided with Core
Documentation
Product Specification
Design File Formats VHDL/EDIF
Constraints File
N/A
Verification
N/A
Instantiation Template N/A
Reference Designs
None
Design Tool Requirements
Xilinx Implementation ISE® 11.1 or later
Tools
Verification
ChipScope Pro 11.1 or later
Simulation
Not Supported in Simulation
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countries. All other trademarks are the property of their respective owners.
DS283 April 7, 2009
www.xilinx.com
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Product Specification