DS258 Datasheet, PDF (1/12 Pages) Xilinx, Inc – Fully synchronous operation

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8b/10b Decoder v7.1
DS258 April 28, 2005
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Product Specification
Features
• Drop-in module for Virtex™, Virtex-E, Virtex-II,
Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE,
and Spartan-3 FPGAs
• Decoding of 10-bit symbols into 8-bit bytes and an
accompanying K bit
• Decoding of 268 unique transmitted characters: 256
byte values and 12 special (K) characters
• Fully synchronous operation
• Decoder tracks running disparity to verify that
disparity sequence of the received symbols is valid
• Choice of an LUT-based implementation, which
uses FPGA slices, or a block-memory-based
implementation that uses one of the dedicated
on-chip block memory blocks
• Optional RUN_DISP output tracks the running
disparity of the decoder
• Optional DISP_ERR output indicates a violation of
the running disparity rules
• Optional SINIT input forces the decoder into a
user-defined known state
• Optional CE input can be used to selectively enable
or stall the decoder
• Optional DISP_IN supports chaining multiple
decoders together
• Optional CODE_ERR output indicates that the
input symbol did not correspond to a valid member
of the code set
• Optional SYM_DISP output provides disparity
information on the current symbol being decoded
• Optional ND (new data) output indicates DOUT
has a new decoded symbol on its output
• Block RAM implementation can implement
secondary (B) decoder with almost no additional
resource overhead
• To be used with v7.1i and later of the Xilinx CORE
Generator™ system
Figure Top x-ref 1
DIN[9:0] DOUT[7:0]
DISP_IN
KOUT
SYM_DISP[1:0]
SINIT
RUN_DISP
CE
CODE_ERR
DISP_ERR
CLK
ND
X9164
Figure 1: Decoder Schematic Symbol
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DS258 April 28, 2005
www.xilinx.com
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Product Specification