DS212 Datasheet, PDF (1/11 Pages) –

DS212 February 3, 2015
IEEE 802.16 Compatible
Turbo Product Code Decoder v1.1
Product Specification
Features
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Performs decoding for the turbo product codes
listed in the IEEE 802.16 and 802.16a standards
Optimized for Virtex®-II and Virtex-II Pro FPGAs
using structural VHDL and relationally placed
D_{macro (RPM) technology for maximum and}
predictable performance. Spartan-3 and Virtex-4
device families are supported with a non-RPM
version.
is _{Based on the Comtech AHA Corporation (AHA)}
TPC Galaxy Core
Supports block sizes from 64 bits to 4 Kbits, 64
c _{possible product codes}
Four-SISO option achieves a data rate of 155 Mbps
o _{with five iterations using (64,57)2 code}
(in Virtex-II FPGAs)
n Single-SISO option achieves a data rate of 45 Mbps
with five iterations using (64,57)² code
(in Virtex-II FPGAs)
t _{Provides more than 7 dB of coding gain at 10-6 BER}
i compared to uncoded BPSK in an AWGN channel
n _{Provides up to 10 dB of coding gain over Reed-}
Solomon concatenated with Viterbi in an MMDS
fading channel at a BER of 10^-6
u _{Separate input and output enables plus internal}
buffering allow flexible handling of data flow
e _{Four-SISO option requires 3313 slices, 17 block}
RAMs, and 16 hardware multipliers (in Virtex-II/
Virtex-II Pro FPGAs)
d _{Single-SISO option requires 1062 slices, 13 block}
RAMs, and 4 hardware multipliers (in Virtex-II/
Virtex-II Pro FPGAs)
I Maximum clock rate of 150 MHz in Virtex-II (-6),
P ^{170 MHz in Virtex-II Pro (-7), 111 MHz in Spartan-3}
latency, high code rates, high spectral efficiency, and a
high degree of forward error correction capability.
Turbo product codes offer a higher performance alter-
native to Reed-Solomon or Reed-Solomon concate-
nated with Viterbi error correction methods.
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex-II, Virtex-II Pro, Virtex-4,
and Spartan-3
Resources Used (Virtex-II)
Core Option
I/O
LUTs
FFs
Block
RAMs
Four-SISO
75 6350 5572 17
Single-SISO
75 1943 1780 13
Special Features
RPM
Provided with Core
Documentation
Product Specification
Design File Formats
Encrypted EDIF
Constraints File
.ucf (user constraints file)
Verification
VHDL Test Bench
Instantiation Template
VHDL Wrapper
Design Tool Requirements
Xilinx Implementation
Tools
ISE 4.2.03i or later
Verification
Mentor Graphics®
ModelSim® PE 5.4e
Simulation
Mentor Graphics
ModelSim PE 5.4e
Synthesis
None
Support
(-5), and 172 MHz in Virtex-4 (-10) FPGAs
Provided by Xilinx, Inc.
Applications
The TPC decoder core operates in local multi-point
distribution service (LMDS) and multi-channel, multi-
point distribution service (MMDS) communication
systems. The core is especially useful for those
communication links that require high data rates, low
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DS212 February 3, 2015
www.xilinx.com
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Product Specification