DS208 Datasheet, PDF (1/13 Pages) Xilinx, Inc – LogiCORE IP Initiator/Target

DS208 April 19, 2010
LogiCORE IP Initiator/Target
v5 and v6 for PCI-X
Product Specification
Introduction
The LogiCORE™ IP Initiator/Target v5 and v6 for
PCI^®-X core interface is a pre-implemented and fully
tested module for Xilinx^® FPGAs. Critical paths are con-
trolled by constraints files to ensure predictable timing.
This significantly reduces engineering time required to
implement the PCI-X portion of your design.
The core meets the setup, hold, and clock-to-timing
requirements as specified in the PCI-X specification.
The interface is carefully optimized for best possible
performance and utilization in Xilinx FPGA devices.
Features
• Fully 2.0 Mode 1 compliant LogiCORE IP for
PCI-X, 64-bit, 133/66 MHz interface with 3.3V
operation
• 3.0-compliant core for PCI up to 33 MHz
• Customizable, programmable, single-chip solution
• Pre-defined implementation for predictable timing
• Incorporates Xilinx Smart-IP™ Technology
• Fully verified design tested with Xilinx proprietary
test bench and hardware
• Available through the Xilinx CORE Generator™
software v12.1 with applicable service pack
• Integrated extended capabilities:
♦ PCI-X Capability Item
♦ Power Management Capability Item
♦ Message Signaled Interrupt Capability Item
• Supported functions for PCI-X
♦ Split Completion
♦ Memory Read DWORD
♦ Memory Read Block
♦ Memory Write Block
• Supported functions for PCI
♦ Memory Read
♦ Memory Read Multiple
♦ Memory Read Line
• Memory Write and Invalidate
LogiCORE IP Facts
Core Specifics
Supported Device
Family
See Table 1, page 2.
Resources
Used ⁽¹⁾
LUTs
1748 1469 2310 1868
Slice Flip Flops
1109
954
1504 1350
IOB Flip Flops
94
257
253
253
IOBs
94
90
90
90
BUFGs / DCMs
2/1
2/0
1/1
2/0
Provided with Core
Documentation
Getting Started Guide v6
Getting Started Guide v5
User Guide v6
User Guide v5
Design File
Formats
Verilog/VHDL Simulation Model
NGC Netlist (v6 core only)
NGO Netlist (v5 core only)
Constraints Files
User Constraints Files (UCF)
Example Design
VHDL
Verilog
Design Tool Requirements
Xilinx
Implementation
Tools
ISE® 12.1i
Verification
Mentor Graphics® ModelSim® v6.5c and
above
Simulation
Mentor Graphics ModelSim v6.5c and
above
Synopsys VCS and VCS MX 2009.12 and
above
Cadence® Incisive Enterprise Simulator (IES)
v9.2 and above
Synthesis
XST
Synplicity® Synplify Pro® D-2009.12
Support
Provided by Xilinx, Inc.
1. Resource utilization depends on configuration of the interface and
the user design. Unused resources are trimmed by the Xilinx tech-
nology mapper. The utilization figures reported in this table are
representative of a maximum configuration.
© 2002–2010 Xilinx, Inc., XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS208 April 19, 2010
www.xilinx.com
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Product Specification