DS206 Datasheet, PDF (1/13 Pages) Xilinx, Inc – LogiCORE IP 32-Bit

DS206 October 16, 2012
LogiCORE IP 32-Bit
Initiator/Target
v3 & v4 for PCI
Product Specification v3.167 & v4.18
Features
• Fully compatible 32-bit, 66/33 MHz
Initiator/Target core for PCI™
• Customizable, programmable, single-chip solution
• Pre-defined implementation for predictable timing
• Incorporates Xilinx Smart-IP technology
• 3.3V operation at 0–66 MHz
• Fully verified design tested with Xilinx proprietary
test bench and hardware
• Delivered through the Xilinx^® CORE Generator™
tool and Vivado™ IP Catalog
• CardBus compliant
• Supported initiator functions:
• Configuration read, configuration write
• Memory read, memory write, MRM, MRL
• Interrupt acknowledge, special cycles
• I/O read, I/O write
• Supported target functions:
• Type 0 configuration space header
• Up to three base address registers (MEM or
I/O with adjustable block size from 16 bytes to
2 GB)
• Medium decode speed
• Parity generation, parity error detection
• Configuration read, configuration write
• Memory read, memory write, MRM, MRL
• Interrupt acknowledge
• I/O read, I/O write
• Target abort, target retry, target disconnect
LogiCORE IP Facts Table
Core Specifics
Supported Device
Family⁽¹⁾
See Table 1.
Resources Used⁽²⁾
v4 Core
v3 Core
LUTs
506
553
Slice Flip-Flops
333
566
IOB Flip-Flops
270
97
IOBs
55
50
GCLKs ⁽³⁾
2
1
Provided with Core
Documentation
Product Specification v3 & v4
Getting Started Guide v3
User Guide v4
User Guide v3
Design File Formats
ISE: VHDL/Verilog Simulation Model
ISE: NGC Netlist (v4 core only)
ISE: NGO Netlist (v3 core only)
Vivado: Encrypted RTL
Constraints File
ISE: UCF
Vivado: XDC
Test Bench
VHDL/Verilog Example Test Bench
Instantiation Template
VHDL/Verilog Wrapper
Example Design
VHDL/Verilog Example Design
Tested Design Flows⁽⁴⁾
Design Entry
ISE^® Design Suite v14.3
Vivado Design Suite v2012.3⁽⁵⁾
Simulation
Mentor Graphics ModelSim
Cadence Incisive Enterprise Simulator
(IES)
Synthesis
Xilinx XST
Vivado Synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
1. For a complete listing of supported devices, see the release notes
for this core.
2. Depends on configuration of the interface and design. Unused
resources are trimmed by the Xilinx technology mapper. The
utilization figures reported represent a maximum configuration.
3. Virtex^®-4 and Virtex-5 FPGA implementations require additional
BUFG for 200 MHz reference clock.
4. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
5. Supports 7 series devices only.
© Copyright 2010–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS206 October 16, 2012
www.xilinx.com
1
Product Specification v3.167 & v4.18