DS120 Datasheet, PDF (1/3 Pages) Xilinx, Inc – Enhanced pin-locking architecture

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XC9500 In-System Programmable
CPLD Automotive IQ Family
DS120-1 (v1.2) October 18, 2004
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Features
• System frequency up to 55 MHz
• Guaranteed to meet full electrical specifications over T_A
= –40 to +125°C
• 5V in-system programmable
- Endurance of 10,000 program/erase cycles
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
- Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
- Programmable power reduction mode in each
macrocell
- Slew rate control on individual outputs
- User programmable ground pin capability
- Extended pattern security features for design
protection
- High-drive 24 mA outputs
- 3.3V or 5V I/O capability
- CMOS 5V Fast FLASH™ technology
- Supports parallel programming of multiple XC9500
devices
• Refer to XC9500 Family data sheet [September 15,
1999 (version 5.0)] for architecture description
• Refer to XC9536 data sheet [December 4, 1998
(version 5.0)] and XC9572XL data sheet [December 4,
1998 (version 3.0)] for pin tables
Family Overview
The XC9500 CPLD Automotive IQ family provides
advanced in-system programming and test capabilities for
high performance, general purpose logic integration. All
devices are in-system programmable for a minimum of
10,000 program/erase cycles. Extensive IEEE 1149.1
(JTAG) boundary-scan support is also included on all family
members.
As shown in Table 1, logic density of the XC9500 devices
ranges from 800 to 1,600 usable gates with 36 and 72 reg-
isters, respectively. Multiple package options and associ-
ated I/O capacity are shown in Table 2. The XC9500 family
is fully pin-compatible allowing easy design migration
across multiple density options in a given package footprint.
The XC9500 architectural features address the require-
ments of in-system programmability. Enhanced pin-locking
capability avoids costly board rework. An expanded JTAG
instruction set allows version control of programming pat-
terns and in-system debugging. In-system programming
throughout the full device operating range and a minimum
of 10,000 program/erase cycles provide worry-free recon-
figurations and system field upgrades.
Advanced system features include output slew rate control
and user-programmable ground pins to help reduce system
noise. I/Os may be configured for 3.3V or 5V operation. All
outputs provide 24 mA drive.
Table 1: XC9500 Device Automotive Family
XC9536
XC9572
Macrocells
36
72
Usable Gates
800
1,600
Registers
36
72
T_PD (ns)
5
7.5
T_SU (ns)
3.5
4.5
T_CO (ns)
4.0
4.5
f_CNT (MHz)⁽¹⁾
100
125
f_SYSTEM (MHz)⁽²⁾
100
83.3
Notes:
1. f_CNT = Operating frequency for 16-bit counters.
2. f_SYSTEM = Internal operating frequency for general
purpose system designs spanning multiple FBs.
Table 2: Available Packages and Device I/O Pins (not
including dedicated JTAG pins)
XC9536
XC9572
44-Pin VQFP
34
-
100-Pin TQFP
-
72
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DS120-1 (v1.2) October 18, 2004
www.xilinx.com
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Product Specification
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