DS119 Datasheet, PDF (1/7 Pages) Xilinx, Inc – High-speed pin-to-pin delays of 10 ns

0
R
XCR3128XL 128 Macrocell
Automotive IQ CPLD
DS119-2 (v1.1) October 18, 2004
0 14 _{Advance Product Specification}
Features
• Guaranteed to meet full electrical specifications over T_A
= –40°C to +125°C
• Technology: 0.35 µm EEPROM process
• Full Boundary Scan Test (IEEE 1149.1) for flexible
in-system device and system testing
• Fast programming times in production saves time and
money
- Increases system reliability through reduced device
handling
• High-speed pin-to-pin delays of 10 ns (100 MHz)
• Slew rate control per output to reduce EMI
• 100% routable which enables all device resources to
be utilized
• Refer to XPLA3 Family data sheet (DS012) for
architecture description
• Refer to XCR3128XL data sheet (DS016) for pin
descriptions
Description
The CoolRunner™ XCR3128XL-Q CPLD Automotive IQ
product is targeted for low power systems that include por-
table, handheld, automotive, and power sensitive applica-
tions. This device includes Fast Zero Power (FZP) design
technology that combines low power and high speed. With
this design technique, the XCR3128XL-Q delivers low
standby current without the need for "turbo bits" or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era) with
a cascaded chain of pure CMOS gates, the dynamic power
is also substantially lower than any other CPLD. CoolRun-
ner devices are the only TotalCMOS PLDs, as they use both
a CMOS process technology and the patented full CMOS
FZP design technique.
The CoolRunner XCR3128XL-Q employs a full PLA struc-
ture for logic allocation within a functon block. The PLA pro-
vides maximum flexibility and logic density, with superior pin
locking capability, while maintaining deterministic timing.
The CoolRunner XCR3128XL-Q is supported by Web-
PACK™ and WebFITTER™ from Xilinx and industry stan-
Table 2: Typical I_CC vs. Frequency at V_CC = 3.3V, 25° C
Frequency (MHz)
0
1
5
10
Typical I_CC (mA)
0.02 0.5 2.2 4.4
dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, ViewLogic, and Synplicity), using text (ABEL,
VHDL, Verilog) and schematic capture design entry. Design
verification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms.
The XCR3128XL-Q features also include industry-stan-
dard, IEEE 1149.1, JTAG interface through which bound-
ary-scan testing and In-System Programming (ISP) and
reprogramming of the device can occur. This device is elec-
trically reprogrammable using industry standard device
programmers.
Table 1: CoolRunner XCR3128XL-Q
XCR3128XL-Q
Macrocells
128
Usable Gates
3,000
Registers
128
F_SYSTEM (MHz)
95
User I/O (100-pin VQFP)
84
User I/O (144-pin TQFP)
108
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Frequency (MHz)
DS016_02_112100
Figure 1: Typical I_CC vs. Frequency at V_CC = 3.3V, 25° C
20
40
60
80 100 120 140
8.7 17.1 25.3 33.6 41.6 49.7 57.7
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS119-2 (v1.1) October 18, 2004
www.xilinx.com
1
Advance Product Specification
1-800-255-7778