DS109 Datasheet, PDF (1/3 Pages) Xilinx, Inc – High-speed pin-to-pin delays of 10 ns

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DS109-1 (v1.3) October 18, 2004
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CoolRunner XPLA3 CPLD
Automotive IQ Product Family
Introduction and Ordering
0 14 _{Advance Product Specification}
Features
• Guaranteed to meet full electrical specifications over
T_A = –40°C to +125°C
• Technology: 0.35 µm EEPROM process
• Full Boundary Scan Test (IEEE 1149.1) for flexible
in-system device and system testing
• Fast programmng times in production saves time and
money
- Increases system reliability through reduced device
handling
• High-speed pin-to-pin delays of 10 ns (100 MHz)
• Slew rate control per output to reduce EMI
• 100% routable which enables all device resources to
be utilized
Family Overview
The CoolRunner™ XPLA3 (extended Programmable Logic
Array) Automotive IQ product family of CPLDs is targeted
for low power systems that include portable, handheld,
automotive, and power sensitive applications. Each mem-
ber of the XPLA3 family includes Fast Zero Power™ (FZP)
design technology that combines low power and high
speed. With this design technique, the XPLA3 family deliv-
ers power that is less than 100 µA at standby without the
need for "turbo bits" or other power down schemes. By
replacing conventional sense amplifier methods for imple-
menting product terms (a technique that has been used in
PLDs since the bipolar era) with a cascaded chain of pure
CMOS gates, the dynamic power is also substantially lower
than any other CPLD. CoolRunner devices are the only
TotalCMOS PLDs, as they use both a CMOS process tech-
nology and the patented full CMOS FZP design technique.
The CoolRunner XPLA3 family employs a full PLA structure
for logic allocation within a functon block. The PLA provides
maximum flexibility and logic density, with superior pin lock-
ing capability, while maintaining deterministic timing.
XPLA3 CPLDs are supported by WebPACK™ and WebFIT-
TER™ from Xilinx and industry standard CAE tools
(Cadence/OrCAD, Exemplar Logic, Mentor, Synopsys,
ViewLogic, and Synplicity), using text (ABEL, VHDL, Ver-
ilog) and schematic capture design entry. Design verifica-
tion uses industry standard simulators for functional and
timing simulation. Development is supported on personal
computer, Sparc, and HP platforms.
The XPLA3 family features also include industry-standard,
IEEE 1149.1, JTAG interface through which boundary-scan
testing and In-System Programming (ISP) and reprogram-
ming of the device can occur. The XPLA3 CPLD is electri-
cally reprogrammable using industry standard device
programmers.
Table 1: CoolRunner XPLA3 Device Family
XCR3032XL XCR3064XL
Macrocells
32
64
Usable Gates
750
1,500
Registers
32
64
F_SYSTEM (MHz)
95
95
XCR3128XL
128
3,000
128
95
XCR3256XL
256
6,000
256
88
XCR3384XL
384
9,000
384
87
XCR3512XL
512
12,000
512
77
Table 2: CoolRunner XPLA3 Packages and User I/O Pins
XCR3032XL XCR3064XL XCR3128XL
44-pin VQFP
100-pin VQFP
144-pin TQFP
208-pin PQFP
36
36
-
-
68
84
-
-
108
-
-
-
XCR3256XL
-
-
120
164
XCR3384XL
-
-
-
172
XCR3512XL
-
-
-
180
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS109-1 (v1.3) October 18, 2004
www.xilinx.com
1
Advance Product Specification
1-800-255-7778