X4003 Datasheet, PDF (8/18 Pages) Xicor Inc. – CPU Supervisor

X4003/X4005
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
Data Output
from Receiver
Start
8
9
Acknowledge
SERIAL WRITE OPERATIONS
Slave Address Byte
Following a start condition, the master must output a
slave address byte. This byte consists of several parts:
– a device type identifier that is always ‘1011’.
– two bits of ‘0’.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the slave address byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 8.
– After loading the entire slave address byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct com-
pare, the device outputs an acknowledge on the SDA
line.
Write Control Register
To write to the control register, the device requires the
slave address byte and a byte address. This gives the
master access to register. After receipt of the address
byte, the device responds with an acknowledge, and
awaits the data. After receiving the 8 bits of the data
byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled,
so the device will not respond to any requests from the
master. If WP is HIGH, the control register cannot be
changed. A write to the control register will suppress
the acknowledge bit and no data in the control register
will change. With WP low, a second byte written to the
control register terminates the operation and no write
occurs.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending 1 full data byte
plus the subsequent ACK signal. If a stop is issued in
the middle of a data byte, or before 1 full data byte plus
its associated ACK is sent, then the device will reset
itself without performing the write.
Figure 8. Write Control Register Sequence
Signals from
the Master
Slave
Address
Byte
Address
Data
SDA Bus
10 11 0 010 1111111 1
Signals from
the Slave
A
A
A
C
C
C
K
K
K
REV 1.1.3 4/30/02
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Characteristics subject to change without notice. 8 of 18