X24001 Datasheet, PDF(8/13 Page) Xicor Inc.

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X24001 Datasheet, PDF (8/13 Pages) Xicor Inc. – Identi™PROM

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X24001

Bus Timing

SCL

SDA IN

tSU:STA

SDA OUT

tHIGH

tLOW

tHD:STA tHD:DAT

tSU:DAT

tAA

tDH

tSU:STO

tBUF

3830 FHD F09

WRITE CYCLE LIMITS

Symbol

tWR(4)

Parameter

Write Cycle Time

Min.

Max.

Units

3830 PGM T09

Write Cycle Timing

SCL

SDA

tWR

START

CONDTION

X24001

ADDRESS

3830 ILL F10.1

Note:

(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters

are periodically sampled and not 100% tested.

(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the

write cycle, the X24001 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start

conditions.

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