X1205 Datasheet, PDF (8/22 Pages) Xicor Inc. – Real Time Clock/Calendar

X1205 – Preliminary Information
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Figure 5. Acknowledge Response From Receiver
SCL from
Master
1
Data Output
from Transmitter
Data Output
from Receiver
Start
Stop
8
9
Acknowledge
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1205 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
REV 1.0.9 8/29/02
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Characteristics subject to change without notice. 8 of 22