X9271 Datasheet, PDF (7/23 Pages) Xicor Inc. – Single Digitally-Controlled (XDCP) Potentiometer

X9271
DEVICE DESCRIPTION
Instructions
IDENTIFICATION BYTE (ID AND A)
The first byte sent to the X9271 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device id for the X9271; this is fixed as 0101[B] (refer to
Table 4).
The A1-A0 bits in the ID byte is the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9271 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9271 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
be actively driven by CMOS input signals or tied to V_CC
or V_SS.
INSTRUCTION BYTE (I[3:0])
The next byte sent to the X9271 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[3:0]). The RB and RA bits point to one of the
four Data Registers. P0 is the POT selection; since the
X9271 is single POT, the P0=0. The format is shown in
Table 5.
REGISTER BANK SELECTION (R1, R0, P1, P0)
There are 16 registers organized into four banks. Bank
0 is the default bank of registers. Only Bank 0 registers
can be used for data register to Wiper Counter
Register operations.
Banks 1, 2, and 3 are additional banks of registers (12
total) that can be used for SPI write and read
operations. The data registers in Banks 1, 2, and 3
cannot be used for direct read/write operations
between the Wiper Counter Register.
Register Selection (DR0 to DR3) Table
Register
RB RA Selection
Operations
00
0
Data Register Read and Write;
Wiper Counter Register
Operations
01
1
Data Register Read and Write;
Wiper Counter Register
Operations
10
2
Data Register Read and Write;
Wiper Counter Register
Operations
11
3
Data Register Read and Write;
Wiper Counter Register
Operations
Register Bank Selection (Bank 0 to Bank 3) Table
Bank
P1 P0 Selection
Operations
00
0
Data Register Read and Write;
Wiper Counter Register
Operations
01
1
Data Register Read and Write
Only
10
2
Data Register Read and Write
Only
11
3
Data Register Read and Write
Only
Table 4. Identification Byte Format
Device Type
Identifier
Set to 0
for proper operation
Internal
Slave Address
ID3
ID2
ID1
ID0
0
0
1
0
1
(MSB)
0
A1
A0
(LSB)
REV 1.1.7 2/6/03
www.xicor.com
Characteristics subject to change without notice. 7 of 23