X9111 Datasheet, PDF (6/21 Pages) Xicor Inc. – Single Digitally-Controlled Potentiometer

X9111 – Preliminary Information
Table 1. Wiper Latch, WL (10-bit), WCR9–WCR0: Used to store the current wiper position (Volatile, V)
WCR9 WCR8 WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
Table 2. Data Register, DR (10-bit), Bit 9–Bit 0: Used to store wiper positions or data (Non-Volatile, NV)
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
Table 3. Status Register, SR (1-bit)
WIP
(LSB)
DEVICE INSTRUCTIONS
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following
a CS going HIGH to LOW, is called the Identification
Byte. The most significant four bits of the slave address
are a device type identifier. The ID[3:0] bits is the
device ID for the X9111; this is fixed as 0101[B] (refer
to Table 4).
The A1–A0 bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1–A0 input pins. The slave address is
externally specified by the user. The X9111 compares
the serial data stream with the address input state; a
Table 4. Identification Byte Format
Device Type
Identifier
ID3
ID2
ID1
ID0
0
1
0
1
(MSB)
successful compare of the address bits is required for
the X9111 to successfully continue the command
sequence. Only the device whose slave address
matches the incoming device address sent by the
master executes the instruction. The A1–A0 inputs can
be actively driven by CMOS input signals or tied to V_CC
or V_SS. The R/W bit is used to set the device to either
read or write mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown in Table 5.
Internal Slave
Address
Read or
Write Bit
0
A1
A0
R/W
(LSB)
Table 5. Instruction Byte Format
Instruction
Opcode
Register
Selection
I2
I1
I0
0
RB
RA
0
0
(MSB)
RB
RA
Register
0
0
0
1
1
0
1
1
DR0
DR1
DR2
DR3
(LSB)
REV 1.1.15 5/9/03
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Characteristics subject to change without notice. 6 of 21