X24640 Datasheet, PDF (6/17 Pages) Xicor Inc. – 400KHz 2-Wire Serial E 2 PROM with Block Lock

X24640
WRITE OPERATIONS
Byte Write
For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any
one of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowl-
edge, and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write
cycle is in progress the device inputs are disabled
and the device will not respond to any requests from
the master. The SDA pin is at high impedance. See
figure 5.
Page Write
The device is capable of a thirty-two byte page write
operation. It is initiated in the same manner as the byte
write operation; but instead of terminating the write
operation after the first data word is transferred, the
master can transmit up to thirty-one more words. The
device will respond with an acknowledge after the
receipt of each word, and then the byte address is
internally incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the current page. This means that the master
can write 32 words to the page beginning at any byte.
If the master begins writing at byte 16, and loads 32
words, then the first 16 words are written to bytes 16
through 31, and the last 16 words are written to bytes
0 through 15. Afterwards, the address counter would
point to byte 16. If the master writes more than 32
words, then the previously loaded data is overwritten
by the new data, one byte at a time.
The master terminates the data byte loading by
issuing a stop condition, which causes the device to
begin the nonvolatile write cycle. As with the byte write
operation, all inputs are disabled until completion of
the internal write cycle. Refer to figure 6 for the
address, acknowledge, and data transfer sequence.
Figure 5. Byte Write Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
A
R
SLAVE
ADDRESS
T
S1 0 1 0
0
WORD ADDRESS WORD ADDRESS
BYTE 1
BYTE 0
A
A
A
C
C
C
K
K
K
DATA
S
T
O
P
P
A
C
K
7038 FM 07
Figure 6. Page Write Sequence
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
S
T
SLAVE
A _ADDRESS
R
T
WORD ADDRESS WORD ADDRESS
BYTE 1
BYTE 0
S 1010
0
A
A
A
C
C
C
K
K
K
DATA
(0)
(0≤n≤31)
DATA
(n)
A
C
K
S
T
O
P
P
A
C
K
7038 FM 08
6