X24026 Datasheet, PDF(6/15 Page) Xicor Inc.

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X24026 Datasheet, PDF (6/15 Pages) Xicor Inc. – Serial E2PROM

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X24026

Page Write

The X24026 is capable of a four byte page write opera-

tion. It is initiated in the same manner as the byte write

operation, but instead of terminating the write cycle after

the ï¬rst data word is transferred, the master can transmit

up to three more words. After the receipt of each word,

the X24026 will respond with an acknowledge.

After the receipt of each word, the two low order address

bits are internally incremented by one. The high order six

bits of the address remain constant. If the master should

transmit more than four words prior to generating the

stop condition, the address counter will âroll overâ and the

previously written data will be overwritten. As with the

byte write operation, all inputs are disabled until comple-

tion of the internal write cycle. Refer to Figure 6 for the

address, acknowledge and data transfer sequence.

Acknowledge Polling

The disabling of the inputs, during the internal write oper-

ation, can be used to take advantage of the typical 5 ms

write cycle time. Once the stop condition is issued to indi-

cate the end of the hostâs write operation the X24026 ini-

tiates the internal write cycle. ACK polling can be initiated

immediately. This involves issuing the start condition fol-

lowed by the slave address for a write operation. If the

X24026 is still busy with the write operation no ACK will

be returned. If the X24026 has completed the write oper-

ation an ACK will be returned and the master can then

proceed with the next read or write operation.

READ OPERATIONS

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of the

slave address is set to a one. There are three basic read

operations: current address read, random read and

sequential read.

It should be noted that the ninth clock cycle of the read

operation is not a âdonât care.â To terminate a read opera-

tion, the master must either issue a stop condition during

the ninth cycle or hold SDA HIGH during the ninth clock

cycle and then issue a stop condition.

Flow 1. ACK Polling Sequence

WRITE OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE

START

ISSUE SLAVE_

ADDRESS AND R/W = 0

ACK

RETURNED?

YES

OPERATION

A WRITE?

YES

ISSUE BYTE

ADDRESS

ISSUE STOP

PROCEED

7020 FRM 09

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