X84161 Datasheet, PDF (2/18 Pages) Xicor Inc. – uPort Saver EEPROM

X84161/641/129
PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:
CE
I/O
WP
VSS
8-LEAD PDIP
8-LEAD SOIC
1
8
2 _X84161 7
3 X84641 ⁶
4
5
.230 in.
CE
I/O
NC
NC
NC
WP
VSS
14-LEAD SOIC
1
14
2
13
3
12
4
11
X84129
5
10
6
9
7
8
.230 in.
VCC
NC
OE ^{.190 in.}
NC
V_CC
CE
I/O
WE
8-LEAD TSSOP
1
8
2
3
X84161
7
6
4
5
.252 in.
NC
V _CC
NC
CE
NC
I/O
NC
NC
NC
NC
NC
NC ^{.390 in. WP}
OE
VSS
NC
WE
NC
NC
CE
CE
CE
I/O
NC
NC
NC
WP
V_SS
NC
NC
NC
20-LEAD TSSOP
1
20
2
19
3
18
4
17
5
X84641
16
6
15
7
14
8
13
9
12
10
11
.252 in.
28-LEAD TSSOP
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
X84129
21
9
20
10
19
11
18
12
17
13
16
14
15
. 252 in.
OE
WE
WP
VSS
.114 in.
NC
NC
VCC
NC
NC
NC
.250 in.
NC
OE
WE
NC
NC
NC
NC
NC
V_CC
NC
NC
NC
.394 in.
NC
OE
WE
NC
NC
NC
PIN NAMES
I/O Data Input/Output
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
WP Write Protect Input
V_CC Supply Voltage
V_SS Ground
NC No Connect
7008 FRM T01
PACKAGE
SELECTION GUIDE
84161
84641
84129
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
8-Lead PDIP
14-Lead SOIC
28-Lead TSSOP
7008 FRM T0A
7008 FRM F01
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the out-
put buffer and to read data from the device on the I/O line.
Write Enable (WE)
The Write Enable input must be LOW to write either data
or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to or
serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func-
tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW will
have no effect on the cycle already underway, but will
inhibit any additional nonvolatile write cycles.
2