X9530 Datasheet, PDF (16/30 Pages) Xicor Inc. – Temperature Compensated Laser Diode Controller

X9530
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 13.). This byte
includes three parts:
– The four MSBs (SA7-SA4) are the Device Type
Identifier, which must always be set to 1010 in order
to select the X9530.
– The next three bits (SA3-SA1) are the Device
Address bits (AS2-AS0). To access any part of the
X9530’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
– The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write
operation (Refer to Figure 13.)
Figure 14. Acknowledge Polling Sequence
Byte load completed by issuing
STOP. Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK returned?
YES
High Voltage
complete. Continue command
sequence.
YES
Continue normal Read or Write
command sequence
NO
Issue STOP
PROCEED
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is
correctly issued (including the final STOP condition),
the X9530 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time, any
Read or Write command is ignored by the X9530.
Write Acknowledge Polling is used to determine
whether a high voltage write cycle is completed.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X9530’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage cycle,
then no ACK is returned. If the high voltage cycle is
completed, an ACK is returned and the master can
then proceed with a new Read or Write operation.
(Refer to Figure 14.).
Byte Write Operation
In order to perform a Byte Write operation to the
memory array, the Write Enable Latch (WEL) bit of the
Control 6 Register must first be set to “1”. (See “WEL:
Write Enable Latch (Volatile)” on page 7.)
For any Byte Write operation, the X9530 requires the
Slave Address Byte, an Address Byte, and a Data Byte
(See Figure 15). After each of them, the X9530
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
all data bits are volatile, the X9530 is ready for the next
read or write operation. If some bits are nonvolatile, the
X9530 begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X9530 does not respond to any requests from the
master. The SDA output is at high impedance.
A Byte Write operation can access bytes at locations
00h through FEh directly, when setting the Address
Byte to 00h through FEh respectively. Setting the
Address Byte to FFh accesses the byte at location
100h. The other sixteen bytes, at locations FFh and
101h through 10Fh can only be accessed using Page
Write operations. The byte at location FFh can only be
written using a “Page Write” operation.
Writing to Control bytes which are located at byte
addresses 80h through 8Fh is a special case
described in the section “Writing to Control Registers”.
REV 3.7 8/26/04
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Characteristics subject to change without notice. 16 of 30