X4043 Datasheet, PDF (16/25 Pages) Intersil Corporation – CPU Supervisor with 4kbit EEPROM

X4043/45
TIMING DIAGRAMS
Bus Timing
t_F
t_HIGH
SCL
t_SU:STA
SDA IN
t_HD:STA
t_SU:DAT
t_LOW
t_HD:DAT
SDA OUT
t_R
t_AA t_DH
WP Pin Timing
SCL
START
SDA IN
WP
t_SU:WP
Clk 1
Slave Address Byte
Clk 9
t_HD:WP
t_SU:STO
t_BUF
Write Cycle Timing
SCL
SDA
8^th Bit of Last Byte
ACK
t_WC
Stop
Condition
Start
Condition
Nonvolatile Write Cycle Timing
Symbol
t_WC⁽⁷⁾
Parameter
Write cycle time
Min.
Typ.⁽⁷⁾
5
Max.
10
Unit
ms
Notes: (7) t_WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used.
REV 1.1.17 9/14/01
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Characteristics subject to change without notice. 16 of 25