X4283 Datasheet, PDF (1/22 Pages) Xicor Inc. – CPU Supervisor with 128K EEPROM

Preliminary Information
128K
X4283/85
16K x 8 Bit
CPU Supervisor with 128K EEPROM
FEATURES
• Selectable watchdog timer
• Low V_CC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low V_CC reset threshold voltage using
special programming sequence
—Reset signal valid to V_CC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 128Kbits of EEPROM
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock^™ protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead TSSOP
DESCRIPTION
The X4283/85 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Block Lock protect serial
EEPROM memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the RESET/
RESET signal. The user selects the interval from three
preset values. Once selected, the interval does not
change, even after cycling the power.
The device’s low V_CC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V_CC falls below the set minimum V_CC
trip point. RESET/RESET is asserted until V_CC returns
to proper operating level and stabilizes. Four industry
BLOCK DIAGRAM
WP
SDA
SCL
S0
S1
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
V_CC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
V_CC
+
V_TRIP
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power on and
Low Voltage
Reset
Generation
RESET (X4283)
RESET (X4285)
REV 1.17 11/27/00
www.xicor.com
Characteristics subject to change without notice. 1 of 22