X28C512 Datasheet, PDF (1/25 Pages) Xicor Inc. – 5 Volt, Byte Alterable E2PROM

X28C512/X28C513
512K
X28C512/X28C513
5 Volt, Byte Alterable E²PROM
64K x 8 Bit
FEATURES
• Access Time: 90ns
• Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or V_PP Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
—Active: 50mA
—Standby: 500µA
• Software Data Protection
—Protects Data Against System Level
Inadvertant Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
• Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
• Two PLCC and LCC Pinouts
—X28C512
—X28C010 E²PROM Pin Compatible
—X28C513
—Compatible with Lower Density E²PROMs
DESCRIPTION
The X28C512/513 is an 64K x 8 E²PROM, fabricated
with Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C512/513 is a 5V only device.
The X28C512/513 features the JEDEC approved pinout
for bytewide memories, compatible with industry stan-
dard EPROMS.
The X28C512/513 supports a 128-byte page write op-
eration, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512/513 also features DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512/513 supports the Software Data
Protection option.
PIN CONFIGURATIONS
PLASTIC DIP
CERDIP
FLAT PACK
SOIC (R)
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8
25
X28C512
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
3856 FHD F01
A11
1
A9
2
A8
3
A13
4
A14
5
NC
6
NC
7
NC
8
WE
9
VCC
10
NC
11
NC
12
NC
13
NC
14
A15
15
A12
16
A7
17
A6
18
A5
19
A4
20
TSOP
X28C512
40
OE
39
A10
38
CE
37
I/O7
36
I/O6
35
I/O5
34
I/O4
33
I/O3
32
NC
31
NC
30
VSS
29
NC
28
NC
27
I/O2
26
I/O1
25
I/O0
24
A0
23
A1
22
A2
21
A3
PGA
I/O0 I/O2 I/O3 I/O5 I/O6
15 17 19 21 22
A1
A0
I/O1 VSS I/O4 I/O7 CE
13
14
16
18
20
23
24
A2
A3
12
11
A10 OE
25 26
A4
A5
10
9
A6
A7
8
7
BOTTOM
VIEW
A11 A9
27 28
A8
A13
29 30
A12 A15 NC VCC NC NC A14
6
5
2
36
34
32
31
NC NC NC WE NC
4
3
1
35
33
3856 ILL F22
3856 FHD F02
PLCC / LCC
30
A7
A6
5 ^{4 3 2 32 31} 29
6
1
28
A14
A13
A5 7
27 A8
A4
A3
8
26
9
X28C512
(TOP VIEW)
25
A9
A11
A2 10
24 OE
A1 11
23 A10
A0 12
22 CE
I/O0
13
14
15 16 17 18 19 20 ₂₁
I/O7
3856 FHD F03
30
A6
A5
5 ^{4 3 2 32 31} 29
6
1
28
A8
A9
A4 7
27 A11
A3
A2
8
26 NC
9
X28C513
(TOP VIEW)
25
OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
14
15 16 17 18 19 20 ₂₁
I/O6
3856 FHD F04
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3856-3.2 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice