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X25642 Datasheet, PDF (1/16 Pages) Xicor Inc. – Advanced SPI Serial E 2 PROM with Block Lock TM Protection | |||
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APPLICATION NOTE
A V A I LABLE
AN19 ⢠AN38 ⢠AN41 ⢠AN61
64K
X25642
8K x 8 Bit
Advanced SPI Serial E2PROM with Block LockTM Protection
FEATURES
⢠2MHz Clock Rate
⢠Low Power CMOS
â<1µA Standby Current
â<5mA Active Current
⢠2.7V To 5.5V Power Supply
⢠SPI Modes (0,0 & 1,1)
⢠8K X 8 Bits
â32 Byte Page Mode
⢠Block Lock Protection
âProtect 1/4, 1/2 or all of E2PROM Array
⢠Built-in Inadvertent Write Protection
âPower-Up/Down protection circuitry
âWrite Enable Latch
âWrite Protect Pin
⢠Self-Timed Write Cycle
â5ms Write Cycle Time (Typical)
⢠High Reliability
âEndurance: 100,000 cycles
âData Retention: 100 Years
âESD protection: 2000V on all pins
⢠Packages
â8-Lead PDIP
â8-Lead SOIC
â14-Lead SOIC
â20-Lead TSSOP
DESCRIPTION
The X25642 is a CMOS 65,536-bit serial E2PROM,
internally organized as 8K x 8. The X25642 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25642 also features two additional inputs that
provide the end user with added ï¬exibility. By
asserting the HOLD input, the X25642 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25642 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25642 utilizes Xicorâs proprietary Direct WriteTM
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
FUNCTIONAL DIAGRAM
SO
SI
SCK
CS
HOLD
STATUS
REGISTER
COMMAND
DECODE
AND
CONTROL
LOGIC
WRITE
PROTECT
LOGIC
X DECODE
LOGIC
64
64
128
8K BYTE
ARRAY
64 X 256
64 X 256
128 X 256
WRITE
CONTROL
AND
WP
TIMING
LOGIC
Direct Write⢠and Block Lock⢠Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
1
3132-1.0 1/17/97 T5/C0/D1 SH
32
8
Y DECODE
DATA REGISTER
3132 ILL F01.1
Characteristics subject to change without notice
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