WM8983_10 Datasheet, PDF (98/124 Pages) Wolfson Microelectronics plc – Mobile Multimedia CODEC with 1W Speaker Driver

WM8983
Production Data
REGISTER BITS BY ADDRESS
Notes:
1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits).
2. Register bits marked “s "Reser”ed" should not be changed from the default.
REGISTER BIT
ADDRESS
LABEL
0 (00h)
[8:0] RESET
DEFAULT
DESCRIPTION
N/A
Software reset
1 (01h)
8
BUFDCOPEN
0
7
OUT4MIXEN
0
6
OUT3MIXEN
0
5
PLLEN
0
4
MICBEN
0
3
BIASEN
0
2
BUFIOEN
0
1:0 VMIDSEL
00
2 (02h)
8
ROUT1EN
0
7
LOUT1EN
0
6
SLEEP
0
5
BOOSTENR
0
4
BOOSTENL
0
Dedicated buffer for DC level shifting output
stages when in 1.5x gain boost configuration.
0 = Buffer disabled
1 = Buffer enabled (required for 1.5x gain boost)
OUT4 mixer enable
0=disabled
1=enabled
OUT3 mixer enable
0=disabled
1=enabled
PLL enable
0=PLL off
1=PLL on
Microphone Bias Enable
0 = OFF (high impedance output)
1 = ON
Analogue amplifier bias control
0=disabled
1=enabled
Unused input/output tie off buffer enable
0=disabled
1=enabled
Reference string impedance to VMID pin
(Determines startup time):
00 = off (250kΩ VMID to AGND1)
01 = 100kΩ
10 = 500kΩ
11 = 10kΩ total (for fast start-up)
ROUT1 output enable
0=disabled
1=enabled
LOUT1 output enable
0=disabled
1=enabled
0 = normal device operation
1 = residual current reduced in device standby
mode
Right channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
Left channel Input BOOST enable
0 = Boost stage OFF
1 = Boost stage ON
REFER TO
Resetting the
Chip
Analogue
Outputs
Power
Management
Power
Management
Master Clock
and Phase
Locked Loop
(PLL)
Input Signal
Path
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
Power
Management
w
PD, Rev 4.3, May 2010
98