WM8777_05 Datasheet, PDF (80/103 Pages) Wolfson Microelectronics plc – 24-bit, 192kHz AV Receiver on-a-Chip

WM8777
Pre-Production
REGISTER
BIT
ADDRESS
LABEL
DEFAULT
DESCRIPTION
5:4
PAIFRX_WL
[1:0]
10
Input Word Length
00 = 16-bit Mode
01 = 20-bit Mode
10 = 24-bit Mode
11 = 32-bit Mode (not supported in right justified mode)
6
MCLKOPEN
0
MCLK pin output enable
0 = MCLK pin is an input
1 = MCLK pin is an output (see MCLKOUTSRC below)
7
MCLKOUTSRC
0
MCLK pin output source
0 = PLL
1 = Crystal clock output.
0011001
(19h)
2:0 PAIFTX_RATE
[2:0]
010
Master Mode MCLK:PDATAOPLRC ratio select:
000 = 128fs
Master Mode
Control
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
3
DACOSR
0
DAC oversample rate select:
0 = 128x oversampling
1 = 64x oversampling
6:4 PAIFRX_RATE
[2:0]
010
Master Mode MCLK:PDATAIPLRC ratio select:
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
7
PAIFTX_MS
0
Master/Slave Interface mode select. If ADCCLKSRC is set high
then this register control whether the ADC clocks are in master or
slave mode/
0 = Slave Mode – PDATAOPLRC and ADCPBCLK are inputs
1 = Master Mode – PDATAOPLRC and ADCPBCLK are outputs
8
PAIFRX_MS
0
Maser/Slave interface mode select
0 = Slave Mode – PDATAOPLRC, PDATAIPLRC and PBCLK are
inputs
1 = Master Mode – PDATAOPLRC, PDATAIPLRC and PBCLK
are outputs
Note if ADCCLKSRC is set high then this register only controls
PDATAIPLRC and PBCLK.
0011010
0
(1Ah)
Powerdown
Control
PWDN
0
Chip Powerdown Control (works in tandem with the other
powerdown registers):
0 = All digital circuits running, outputs are active
1 = All digital circuits in power save mode, outputs
muted
1
ADCPD
1
ADC powerdown:
0 = ADC enabled
1 = ADC disabled
5:2
DACPD[3:0]
1111
DAC powerdowns (0 = DAC enabled, 1 = DAC disabled)
DACPD[0] = DAC1
DACPD[1] = DAC2
DACPD[2] = DAC3
DACPD[3] = DAC4
w
PP Rev 3.0 January 2004
80