WM8785_06 Datasheet, PDF (8/31 Pages) Wolfson Microelectronics plc – 24-Bit, 192kHz Stereo ADC

WM8785
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Production Data
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25^oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock cycle time
MCLK duty cycle
SYMBOL
TMCLKY
TMCLKDS
MIN
25
60:40
TYP
MAX
UNIT
ns
40:60
AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25^oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
SYMBOL
tDL
tDDA
MIN
TYP
MAX
UNIT
0
10
ns
0
11
ns
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PD Rev 4.1 December 2006
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