WM8738_06 Datasheet, PDF (8/18 Pages) Wolfson Microelectronics plc – 24 Bit Stereo ADC

WM8738
DIGITAL AUDIO INTERFACE TIMING
t
MCLKL
MCLK
t
MCLKH
t_MCLKY
Figure 1 Master Clock Timing Requirements
Production Data
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKH
TMCLKL
TMCLKY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
ns
10
ns
27
ns
BCLK
t_BCH
t_BCL
t
BCY
L RC L K
SDATO
t_DD
t_LRH
t
LRS U
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
tBCY
BCLK pulse width high
tBCH
BCLK pulse width low
tBCL
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
tLRH
BCLK rising edge
SDATO propagation delay
tDD
from BCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
80
ns
40
ns
40
ns
10
ns
10
ns
10
ns
w
PD Rev 4.4 August 2006
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