WM2148 Datasheet, PDF (8/14 Pages) Wolfson Microelectronics plc – 14-bit 8MSPS Analogue-To-Digital Converter

WM2148
Production Data
DEVICE DESCRIPTION
INTRODUCTION
The WM2184 is a fast, low-power 14-bit ADC designed for leading edge telecommunications
applications such as xDSL front-ends. It consists of a high bandwidth programmable gain input
stage, a high resolution ADC, a parallel control interface, and internal voltage reference circuitry. Its
fully differential design gives it excellent noise immunity.
The analogue signal first enters the programmable gain amplifier (PGA), whose gain can be
controlled in 1dB steps between 0dB and 7dB, using the PGA gain register. The signal is then
digitised with respect to the two reference voltages, VREF+ and VREFí, in the ADC core. To
compensate for DC offsets in the system, a programmable value of between -128 and +127 LSBs
can be added to the digitised data. This is achieved by writing the offset value to the offset register
and setting the DCO bit (bit 7) in the control register.
Two different output formats are supported to suit the user’s needs. In unsigned binary format, an all-
zero output represents the minimum analogue input level, while in two’s complement format it refers
to the middle level between minimum and maximum (see Table 1, below).
ANALOGUE INPUT
DIGITAL OUTPUT
(Unsigned Binary)
Minimum
Midrange
Maximum
¨9IN = - ¨9REF
¨9IN = 0
¨9IN = ¨9REF
0
8192
16383
Table 1 Unsigned Binary vs Two’s Complement Output Format
DIGITAL OUTPUT
(Two’s Complement)
-8192
0
8191
The out-of-range indicator (OVI) output indicates that the analogue input signal is out of range. It is
asserted whenever the differential input voltage ¨9IN exceeds the differential reference voltage ¨9REF
or í¨9REF. This signal is updated simultaneously with the digital data outputs and is subject to the
same pipeline delay. It can be used to adjust the gain of the internal PGA to prevent the ADC from
clipping.
The WM2148 incorporates a differential voltage reference circuit based on a 1.5V bandgap
reference. The two reference voltages derived from the bandgap, VREF+ and VREFí, are two-thirds
above and below the bandgap voltage VBG, at 2.5V and 0.5V respectively. The analogue input range
is between the two references. To use an external reference, the on-chip bandgap circuit is disabled
by setting the REF bit (bit 12) in the control register. The external reference voltage can then be
applied at the VBG pin. VREF+ and VREFí are still buffered in the same by the internal reference
amplifiers, such that:
V_{REF +}
= V_BG
× 1+

2 _
3_
and
V_{REF −}
= V_BG
× 1 −

2 _
3_
For best performance, VBG, VREF+,VREFí and CML (reference midpoint, pin 4) should all be separately
decoupled (see Recommended External Components).
The WM2184 requires a single 3.3V supply voltage. In Power Down mode, the supply to all analogue
circuitry in the device is switched off, reducing standby current to 20µA provided that the clock is
stopped (a running clock will increase the power consumption of the digital sections).
CONTROL INTERFACE
All functions of the WM2184 are accessed through its parallel interface. There are four internal
registers to retrieve the ADC conversion data, set the device gain and DC offset, and control other
features such as Power Down, reference voltage and output format.
The parallel interface of the WM2148 features three-state buffers for direct connection to a shared
data bus. Driving the OEB pin low enables the output buffers.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
8