WM8775_06 Datasheet, PDF (7/39 Pages) Wolfson Microelectronics plc – 24-bit, 96kHz ADC with 4 Channel I/P Multiplexer

Production Data
WM8775
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
MASTER CLOCK TIMING
MCLK
t_MCLKL
t_MCLKH
t_MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width
high
tMCLKH
MCLK System clock pulse width
low
tMCLKL
MCLK System clock cycle time
tMCLKY
MCLK Duty cycle
Power-saving mode activated
Normal mode resumed
TEST CONDITIONS
After MCLK stopped
After MCLK re-started
MIN
11
11
28
40:60
2
0.5
TYP
MAX
UNIT
1000
60:40
10
1
ns
ns
ns
µs
MCLK
cycle
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered. In this power-saving mode, all
registers will retain their values and can be accessed in the normal manner through the control interface.
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PD Rev 4.1, June 2006
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