WM8762_06 Datasheet, PDF (7/15 Pages) Wolfson Microelectronics plc – 24-bit 192kHz Stereo DAC

WM8762
MASTER CLOCK TIMING
MCLK
t_MCLKL
t_MCLKH
t_MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
System Clock Timing Information
MCLK Master clock pulse width high
tMCLKH
8
MCLK Master clock pulse width low
tMCLKL
8
MCLK Master clock cycle time
tMCLKY
20
MCLK Duty cycle
40:60
Time from MCLK stopping to power
1.5
down.
DIGITAL AUDIO INTERFACE
t_BCH
t_BCL
BCKIN
t_BCY
LRCIN
DIN
t_DS
t_LRH
t_LRSU
t_DH
Production Data
MAX
60:40
12
UNIT
ns
ns
ns
µs
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25^oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
40
ns
BCKIN pulse width high
tBCH
16
ns
BCKIN pulse width low
tBCL
16
ns
LRCIN set-up time to BCKIN rising
edge
tLRSU
8
ns
LRCIN hold time from BCKIN rising
tLRH
edge
8
ns
DIN set-up time to BCKIN rising edge
tDS
8
ns
DIN hold time from BCKIN rising edge
tDH
8
ns
w
PD Rev 4.2 July 2006
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