WM8941 Datasheet, PDF (62/96 Pages) Wolfson Microelectronics plc – Mono CODEC with Speaker Driver and Video Buffer

WM8941
Pre Production
REGISTER
ADDRESS
R6
Clock
generation
control
BIT
LABEL
8
CLKSEL
7:5 MCLKDIV
4:2 BCLKDIV
0
MS
Table 45 Clock Control
DEFAULT
DESCRIPTION
1
Controls the source of the clock for all
internal operation:
0=MCLK
1=PLL output
010
Sets the scaling for either the MCLK or
PLL clock output (under control of
CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
000
Configures the BCLK and FRAME output
frequency, for use when the chip is
master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
0
Sets the chip to be master over FRAME
and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs
generated by the WM8941 (MASTER)
LOOPBACK
Setting the ADC_LOOPBACK or DAC_LOOPBACK register bit enables digital loopback. When the
ADC_LOOPBACK bit is set the output data from the ADC audio interface is fed directly into the DAC
data input. When the DAC_LOOPBACK bit is set the output data from the DAC audio interface is fed
directly to the input of the ADC audio interface.
AUDIO SAMPLE RATES
The WM8941 sample rates for the ADC and the DAC are set using the SR register bits. The cut-offs
for the digital filters and the ALC attack/decay times stated are determined using these values and
assume a 256fs master clock rate.
If a sample rate that is not explicitly supported by the SR register settings is required then the
closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,
decay and hold times will scale appropriately.
w
PP, Rev 3.3, December 2007
62