WM8952 Datasheet, PDF (56/72 Pages) Wolfson Microelectronics plc – Mono ADC with Microphone Pre-amplifier

WM8952
REGISTER MAP
Pre Production
ADDR
Register Name
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Default Value (Bin)
Dec Hex
0
00
Software Reset
SOTWARE RESET ON WRITE / CHIP ID ON READ
1000_1001_0100_0000
0
VMIDSEL[1:0]
0000_0000_0000_0000
1
01
Power management 1
0
0
0
0
0
0
0
0
LVLSHIFT_EN AUXEN
PLLEN
MICBEN
BIASEN
DEVICE_REVISION[2:0]
2
02
Power management 2
0
0
0
0
0
0
0
0
0
0
0
BOOSTEN
0
INPPGAEN
0
ADCEN
0000_0000_0000_0000
3
03
Power management 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000_0000_0000_0000
4
04
Audio Interface
0
0
0
0
0
0
0
BCP
FRAMEP
WL[1:0]
FMT[1:0]
0
ALRSWAP
0
0000_0000_0101_0000
5
05
Companding control
0
0
0
0
0
0
0
0
0
0
WL8
0
0
ADC_COMP[1:0]
0
0000_0000_0000_0000
6
06
Clock Gen control
0
0
0
0
0
0
0
CLKSEL
MCLKDIV[2:0]
BCLKDIV[2:0]
0
MS
0000_0001_0100_0000
7
07
Additional control
0
0
0
0
0
0
0
0
0
0
SOFT_START TOGGLE
SR[2:0]
SLOWCLKEN 0000_0000_0000_0000
8
08
GPIO Stuff
0
0
0
0
0
0
0
0
MODE_GPIO
0
OPCLKDIV[1:0]
GPIOPOL
GPIOSEL[2:0]
0000_0000_0000_0000
9
09
Control Interface
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AUTOINC
0
0000_0000_0000_0010
10
0A
Reserved
11
0B
Reserved
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0000_0000_1111_1111
12
0C
Reserved
13
0D
Reserved
14
0E
ADC Control
0
0
0
0
0
0
0
HPFEN
HPFAPP
HPFCUT[2:0]
0
0
0
ADCPOL
0000_0001_0000_0000
15
0F
ADC Digital Vol
0
0
0
0
0
0
0
0
16
10
Notch Filter 1
NF0_UP
NF0_EN
17
11
Notch Filter 2
NF0_UP
0
NF0_A0[13:0]
NF0_A1[13:0]
ADCVOL[7:0]
0000_0000_1111_1111
0000_0000_0000_0000
0000_0000_0000_0000
18
12
Notch Filter 3
NF1_UP
NF1_EN
NF1_A0[13:0]
0000_0000_0000_0000
19
13
Notch Filter 4
NF1_UP
0
NF1_A1[13:0]
0000_0000_0000_0000
20
14
Notch Filter 5
NF2_UP
NF2_EN
NF2_A0[13:0]
0000_0000_0000_0000
21
15
Notch Filter 6
22
16
Notch Filter 7
NF2_UP
NF3_UP
0
NF3_EN
NF2_A1[13:0]
NF3_A0[13:0]
0000_0000_0000_0000
0000_0000_0000_0000
23
17
Notch Filter 8
24
18
Reserved
NF3_UP
NF3_LP
NF3_A1[13:0]
0000_0000_0000_0000
25
19
Reserved
26
1A
Reserved
27
1B
Reserved
28
1C
Reserved
29
1D
Reserved
30
1E
Reserved
31
1F
Reserved
32
20
ALC control 1
33
21
ALC control 2
34
22
ALC control 3
35
23
Noise Gate
36
24
PLL N
37
25
PLL K 1
38
26
PLL K 2
39
27
PLL K 3
40
28
Reserved
ALCGAIN[5:0]
0
ALCSEL
0
0
ALCMAX[2:0]
ALCMIN[2:0]
0
0
0
0
0
0
0
0
ALCHLD[3:0]
ALCLVL[3:0]
0
0
0
0
0
0
0
ALCMODE
ALCDCY[3:0]
ALCATK[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
NGEN
NGTH[2:0]
PLL_POWERDO
0
0
0
0
0
0
0
0
WN
FRACEN
PLL_PRESCALE[1:0]
PLLN[3:0]
0
0
0
0
0
0
0
0
0
0
PLLK[23:18]
0
0
0
0
0
0
0
PLLK[17:9]
0
0
0
0
0
0
0
PLLK[8:0]
0000_0000_0011_1000
0000_0000_0000_1011
0000_0000_0011_0010
0000_0000_0000_0000
0000_0000_0100_1000
0000_0000_0000_1100
0000_0000_1001_0011
0000_0000_1110_1001
41
29
Reserved
42
2A
Spare Register
43
2B
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ALCZC
0
0000_0000_0011_0000
44
2C
Input ctrl
0
0
0
0
0
0
0
MICBVSEL
0
0
0
0
AUXMODE AUX2INPPGA MICN2INPPGA MICP2INPPGA 0000_0000_0000_0010
45
2D
INP PGA gain ctrl
0
0
0
0
0
0
0
0
INPPGAZC INPPGAMUTE
INPPGAVOL[5:0]
0000_0000_0101_0000
46
2E
Reserved
47
2F
ADC BOOST ctrl
0
0
0
0
0
0
0
PGABOOST
0
MICP2BOOSTVOL[2:0]
0
AUX2BOOSTVOL[2:0]
0000_0000_0000_0000
48
30
Reserved
49
31
Thermal Shutdown
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TSDEN
0
0000_0000_0000_0010
50
32
Reserved
51
33
Reserved
52
34
Reserved
53
35
Reserved
54
36
Reserved
55
37
Reserved
56
38
Reserved
Note: Bits marked in green are readable. Other bits are write-only.
w
PP, Rev 3.1, June 2011
56