WM9711 Datasheet, PDF (54/66 Pages) Wolfson Microelectronics plc – LOW POWER AUDIO CODEC FOR PORTABLE APPLICATIONS

WM9711L
Register 1Ch controls the recording gain.
Production Data
REG
ADDR
1Ch
BIT
15
14
LABEL
RMU
GRL
13:8 RECVOLL
7
ZC
6
GRR
5:0
RECVOLR
DEFAULT
DESCRIPTION
REFER TO
1 (mute)
0 (standard)
000000 (0dB)
0 (OFF)
0 (standard)
000000 (0dB)
Mutes audio ADC input
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls left ADC recording volume
Enables zero-cross detector
Selects gain range for PGA of left ADC. 0=0...+22.5dB in
1.5dB steps, 1=-17.25...+30dB in 0.75dB steps
Controls right ADC recording volume
Audio ADC,
Record Gain
Register 20h is a “general purpose” register as defined by the AC’97 specification. Only two bits are implemented in the
WM9711L.
REG
ADDR
20h
BIT
13
7
LABEL DEFAULT
DESCRIPTION
3DE
0 (OFF)
Enables 3D enhancement
LB
0 (OFF)
Enables loopback (i.e. feed ADC output data
directly into DAC)
REFER TO
Audio DACs, 3D Stereo
Enhancement
Intel’s AC’97 Component
Specification, Revision 2.2, page 55
Register 22h controls 3D stereo enhancement for the audio DACs.
REG
ADDR
22h
BIT
5
4
3:0
LABEL
3DLC
3DUC
3DDEPTH
DEFAULT
0 (low)
0 (high)
0000 (0%)
DESCRIPTION
Selects lower cut-off frequency
Selects upper cut-off frequency
Controls depth of 3D effect
REFER TO
Audio DACs,
3D Stereo
Enhancement
Register 24h is for power management additional to the AC’97 specification. Note that the actual state of each circuit block
depends on both register 24h AND register 26h.
REG BIT
ADDR
LABEL
DEFAULT
DESCRIPTION
24h
15 PD15
0*
Disables Crystal Oscillator
14 PD14
0*
Disables left audio DAC
13 PD13
0*
Disables right audio DAC
12 PD12
0*
Disables left audio ADC
11 PD11
0*
Disables right audio ADC
10 PD10
0*
Disables MICBIAS
9
PD9
0*
Disables left headphone mixer
8
PD8
0*
Disables right headphone mixer
7
PD7
0*
Disables speaker mixer
6
PD6
0*
Disables MONO_OUT buffer (pin 33) and phone mixer
5
PD5
0*
Disables OUT3 buffer (pin 37)
4
PD4
0*
Disables headphone buffers (HPOUTL/R)
3
PD3
0*
Disables speaker outputs (LOUT2, ROUT2)
2
PD2
0*
Disables Line Input PGA (left and right)
1
PD1
0*
Disables Phone Input PGA
0
PD0
0*
Disables Mic Input PGA (left and right)
* “0” corresponds to “ON”, if and only if the corresponding bit in register 26h is also 0.
REFER TO
Power
Management
w
PD Rev 4.1 April 2004
54