WM8983 Datasheet, PDF (54/88 Pages) Wolfson Microelectronics plc – Mobile Multimedia CODEC with 1W Speaker Driver

WM8983
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REGISTER BIT
ADDRESS
LABEL
R49
2
SPKBOOST
Output control
R1
8
Power
management
1
BUFDCOPEN
Table 34 Speaker Boost Stage Control
DEFAULT
DESCRIPTION
0
0 = speaker gain = -1;
DC = AVDD1 / 2
1 = speaker gain = +1.5;
DC = 1.5 x AVDD1 / 2
0
Dedicated buffer for DC level shifting
output stages when in 1.5x gain
boost configuration.
0 = Buffer disabled
1 = Buffer enabled (required for 1.5x
gain boost)
SPKBOOST
OUTPUT
STAGE GAIN
OUTPUT DC
LEVEL
0
1x (0dB)
AVDD1/2
1
1.5x (3.52dB) 1.5xAVDD1/2
Table 35 Output Boost Stage Details
OUTPUT STAGE
CONFIGURATION
Inverting
Non-inverting
REGISTER
ADDRESS
R43
Beep control
BIT
LABEL
5
MUTERPGA2INV
4
INVROUT2
3:1 BEEPVOL
0
BEEPEN
DEFAULT
DESCRIPTION
0
Mute input to INVROUT2 mixer
0
Invert ROUT2 output
000
AUXR input to ROUT2 inverter gain
000 = -15dB
001 = -12dB
010 = -9dB
011 = -6dB
100 = -3dB
101 = 0dB
110 = +3dB
111 = +6dB
0
0 = mute AUXR beep input
1 = enable AUXR beep input
Table 36 AUXR – ROUT2 BEEP Mixer Function
ZERO CROSS TIMEOUT
A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs
the gain will automatically update after a timeout period if a zero cross has not occurred. This is
enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 2²¹ * SYSCLK period.
REGISTER
ADDRESS
R7
Additional
Control
BIT
LABEL
DEFAULT
0
SLOWCLKEN 0
Table 37 Timeout Clock Enable Control
DESCRIPTION
Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
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PP Rev 1.1 August 2005
54