WM9712L Datasheet, PDF (53/77 Pages) Wolfson Microelectronics plc – AC97 Audio and Touchpanel CODEC

Production Data
WM9712L
The properties of the GPIOs are controlled through registers 4Ch to 52h, as shown below.
REGISTER BIT LABEL
ADDRESS
4Ch
n
GCn
4Eh
n
GPn
50h
n
GSn
52h
n
GWn
54h
n
GIn
Table 38 GPIO Control
DEFAULT
DESCRIPTION
1
GPIO Pin Configuration
0: Output
1: Input
GC11-15 are always ‘1’
Unused bits GC6-GC10 are always ‘0’
1
GPIO Pin Polarity / Type
0: Active Low
1: Active High
[GIn = pin level XNOR GPn]
Unused bits GP6-GP10 are always ‘1’
0
GPIO Pin Sticky
1: Sticky
0: Not Sticky
Unused bits GS6-GS10 are always ‘0’
0
GPIO Pin Wake-up
1: Wake Up (generate interrupts from this pin)
0: No wake-up (no interrupts generated)
Unused bits GW6-GW10 are always ‘0’
N/A
GPIO Pin Status
Read: Returns status of each GPIO pin
Write: Writing ‘0’ clears sticky bit
Unused bits GI6-GI10 are always ‘0’
The following procedure is recommended for handling interrupts:
When the controller receives an interrupt, check register 54h. For each GPIO bit in descending order
of priority, check if the bit is ‘1’. If yes, execute corresponding interrupt routine, then write ‘0’ to
corresponding bit in 54h. If no, continue to next lower priority GPIO. After all GPIOs have been
checked, check if the interrupt still present or no. If yes, repeat procedure. If no, then jump back to
process that ran before the interrupt.
If the system CPU cannot execute such an interrupt routine, it may be preferable to switch internal
signals (such as PENDOWN) directly onto the GPIO pins. However, in this case the interrupt signals
cannot be made sticky, and more GPIO pins are tied up both on the WM9712L and on the CPU.
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PD Rev 4.5 August 2006
53