WM8956_07 Datasheet, PDF (50/80 Pages) Wolfson Microelectronics plc – Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers

WM8956
CLOCKING AND SAMPLE RATES
Preliminary Technical Data
Figure 34 Clocking Scheme
Clocks for the DACs, the DSP core functions, the digital audio interface and the class D outputs are
all derived from SYSCLK as show in Figure 34.
SYSCLK can either be derived directly from MCLK, or generated from a PLL using MCLK as a
reference. The clock source is selected by CLKSEL. Many commonly-used audio sample rates can
be derived directly from MCLK, while the PLL provides additional flexibility.
The DAC sample rate is selectable, relative to SYSCLK, using DACDIV. In master mode, BCLK is
also derived from SYSCLK via a programmable clock divide (BCLKDIV).
When the GPIO1 pin is configured as a GPIO, a clock derived from SYSCLK can be output on this
pin to provide clocking for other parts of the system. The frequency of this output clock is set by
OPCLKDIV.
A slow clock derived from SYSCLK is used to de-bounce the headphone detect function, and to set
the timeout period for volume updates when zero-cross functions are used. This clock is enabled by
TOEN and its frequency is set by TOCLKSEL.
The class D outputs require a clock, and this is also derived from SYSCLK via a programmable
divider (DCLKDIV) as shown in Figure 34. The class D switching clock should be set between
700kHz and 800kHz.
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PTD, July 2007, Rev 2.1
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