WM8716 Datasheet, PDF (5/21 Pages) Wolfson Microelectronics plc – High Performance 24-bit, 192kHz Stereo DAC

Production Data
SCKI
t_SCKIL
t_SCKIH
WM8716
Figure 2 System Clock Timing Requirements
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25^oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
SCKI System clock pulse width high
SCKI System clock pulse width low
SYMBOL
tSCKIH
tSCKIL
TEST CONDITIONS
MIN
TYP
13
13
MAX
UNIT
ns
ns
ML/I2S (PIN 28)
MC/DM1 (PIN 27)
MD/DM0 (PIN 26)
CSBIWO (PIN 23)
t_MCY
t_MCH
t_MCL
t_MDS
t_MDH
t_MLL
t_MHH
t_MLH
t_MLS
t_CSML
LSB
t_MLCS
Figure 3 Program Register Input Timing
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25^oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Program Register Input Information
MC/DM1 Pulse cycle time
tMCY
100
MC/DM1 Pulse width LOW
tMCL
40
MC/DM1 Pulse width HIGH
tMCH
40
MD/DM0 Hold time
tMDH
40
MD/DM0 Set-up time
tMDS
40
ML/I2S Low level time
tMLL
(See Note 3)
40 +
1SYSCLK
ML/I2S High level time
tMHH
(See Note 3)
40 +
1SYSCLK
ML/I2S Hold time
tMLH
40
ML/I2S Set-up time
tMLS
40
CSBIWO Low to ML/I2S low time
tCSML
10
ML/I2S High to CSBIWO high time
tMLCS
10
Note:
3.
System clock cycle.
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 3.1 April 2001
5