WM8750BL Datasheet, PDF (45/59 Pages) Wolfson Microelectronics plc – Stereo CODEC for Portable Audio Applications

Pre-Production
WM8750BL
CONTROL INTERFACE
SELECTION OF CONTROL MODE
The WM8750BL is controlled by writing to registers through a serial control interface. A control word
consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is
accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control
register. The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin
selects the interface format.
MODE
INTERFACE FORMAT
Low
2 wire
High
3 wire
Table 41 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on
CSB latches in a complete control word consisting of the last 16 bits.
CSB
SCLK
SDIN
latch
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
control register address
control register data bits
Figure 25 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8750BL supports software control via a 2-wire serial bus. Many devices can be controlled by
the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address
of each register in the WM8750BL).
The WM8750BL operates as a slave device only. The controller indicates the start of data transfer
with a high to low transition on SDIN while SCLK remains high. This indicates that a device address
and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next
eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received
matches the address of the WM8750BL and the R/W bit is ‘0’, indicating a write, then the
WM8750BL responds by pulling SDIN low on the next clock pulse (ACK). If the address is not
recognised or the R/W bit is ‘1’, the WM8750BL returns to the idle condition and wait for a new start
condition and valid address.
Once the WM8750BL has acknowledged a correct address, the controller sends the first byte of
control data (B15 to B8, i.e. the WM8750BL register address plus the first bit of register data). The
WM8750BL then acknowledges the first data byte by pulling SDIN low for one clock pulse. The
controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register
data), and the WM8750BL acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8750BL returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
SCLK
START
DEVICE ADDRESS RD / WR ACK CONTROL BYTE 1 ACK CONTROL BYTE 2 ACK
(7 BITS)
BIT
(LOW)
(BITS 15 TO 8)
(LOW)
(BITS 7 TO 0)
(LOW)
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 26 2-Wire Serial Control Interface
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Pre-Production Rev 3.3 January 2007
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