WM8150 Datasheet, PDF (4/24 Pages) Wolfson Microelectronics plc – SINGLE CHANNEL 12 BIT CIS/CCD AFE WITH 4 BIT WIDE OUTPUT

WM8150
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 16MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Max Gain
0.30
Min Gain
3.22
Input signal limits (see Note 2)
VIN
0
VDD
Full-scale transition error
Gain = 0dB;
-50
10
+50
PGA[7:0] = 07(hex)
Zero-scale transition error
Gain = 0dB;
-50
10
+50
PGA[7:0] = 07(hex)
Differential non-linearity
DNL
0.5
1
Integral non-linearity
INL
2
5
Total output noise
Min Gain
0.25
Max Gain
0.70
References
Upper reference voltage
VRT
2.70
Lower reference voltage
VRB
1.45
Input return bias voltage
VRX
1.55
1.65
1.75
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRTB
1.15
1.25
1.35
1
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
20
50
100
VRLC short-circuit current
1.86
2
4.5
VRLC output resistance
2
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
1
RLCDAC resolution
4
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD = 5.0V
AVDD = 5.0V
0.23
0.25
0.27
0.14
0.16
0.20
0.34
0.39
0.44
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
0.20
0.26
0.31
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
AVDD = 5.0V
4.0
4.16
4.3
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
2.56
2.66
2.76
Offset DAC, Monotonicity Guaranteed
Resolution
8
Differential non-linearity
DNL
0.1
0.5
Integral non-linearity
INL
0.25
1
Step size
2.04
Output voltage
Code 00(hex)
Code FF(hex)
-247
+247
-260
+260
-273
+273
Notes:
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input
range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
UNIT
Vp-p
Vp-p
V
mV
mV
LSB
LSB
LSB rms
LSB rms
V
V
V
V
Ω
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
bits
LSB
LSB
mV/step
mV
mV
w
PD Rev 3.0 November 2002
4