WM8985 Datasheet, PDF (39/118 Pages) Wolfson Microelectronics plc – Multimedia CODEC With Class D Headphone and Line Out

Pre-Production
WM8985
The polarity of the output signal can also be changed under software control using the
ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the
ADCOSR128 register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power
operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.
REGISTER
ADDRESS
R14 (0Eh)
ADC Control
BIT
LABEL
0
ADCLPOL
1
ADCRPOL
3
ADCOSR128
Table 14 ADC Control
DEFAULT
DESCRIPTION
0
ADC left channel polarity adjust:
0 = normal
1 = inverted
0
ADC right channel polarity adjust:
0 = normal
1 = inverted
0
ADC oversample rate select:
0 = 64x (lower power)
1 = 128x (best performance)
SELECTABLE HIGH PASS FILTER
A selectable high pass filter is provided and enabled as default. To disable this filter set HPFEN=0.
The filter has two modes controlled by HPFAPP. In Audio Mode (HPFAPP=0) the filter is first order,
with a cut-off frequency of 3.7Hz. In Application Mode (HPFAPP=1) the filter is second order, with a
cut-off frequency selectable via the HPFCUT register. The cut-off frequencies when HPFAPP=1 are
shown in Table 16.
REGISTER
ADDRESS
R14 (0Eh)
ADC Control
BIT
LABEL
6:4
HPFCUT
7
HPFAPP
8
HPFEN
Table 15 ADC Enable Control
DEFAULT
DESCRIPTION
000
Application mode cut-off frequency
See Table 16 for details.
0
Select audio mode or application mode
0 = Audio mode (1^st order, fc = ~3.7Hz)
1 = Application mode (2^nd order, fc =
HPFCUT)
1
High Pass Filter Enable
0 = disabled
1 = enabled
HPFCUT
[2:0]
SR=101/100
8 11.025 12
SR=011/010
fs (kHz)
16 22.05 24
SR=001/000
32 44.1 48
000
82
113 122 82 113 122 82 113 122
001
102 141 153 102 141 153 102 141 153
010
131 180 156 131 180 156 131 180 156
011
163 225 245 163 225 245 163 225 245
100
204 281 306 204 281 306 204 281 306
101
261 360 392 261 360 392 261 360 392
110
327 450 490 327 450 490 327 450 490
111
408 563 612 408 563 612 408 563 612
Table 16 High Pass Filter Cut-off Frequencies (HPFAPP=1)
Note that the High Pass filter values (when HPFAPP=1) are calculated on the assumption that the
SR register bits are set correctly for the actual sample rate as shown in Table 16. Sampling rate
(SR) is enabled by register bits R7[1:3].
w
PP, Rev 3.4, October 2006
39