WM8731_09 Datasheet, PDF (39/64 Pages) Wolfson Microelectronics plc – Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

WM8731 / WM8731L
Production Data
ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8731/L is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are
outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is
expected that these are set low by the audio interface controller when the WM8731/L is powered off
or in standby.
REGISTER
ADDRESS
0000111
Digital Audio
Interface
Format
BIT
LABEL
1:0
FORMAT[1:0]
3:2
IWL[1:0]
4
LRP
5
LRSWAP
6
MS
7
BCLKINV
Table 15 Digital Audio Interface Control
DEFAULT
DESCRIPTION
10
Audio Data Format Select
11 = DSP Mode, frame sync + 2
data packed words
10 = I²S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
0
DACLRC phase control (in left, right
or I²S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I²S mode)
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after DACLRC rising
edge
0 = MSB is available on 1st BCLK
rising edge after DACLRC rising
edge
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
0
Bit Clock Invert
1 = Invert BCLK
0 = Don’t invert BCLK
Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits.
w
PD, Rev 4.8, April 2009
39