WM8580_08 Datasheet, PDF (38/103 Pages) Wolfson Microelectronics plc – Multichannel CODEC with S/PDIF Transceiver

WM8580
Production Data
Figure 23 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024
or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output
will restart immediately from the current input sample.
All other means of muting the DAC channels will cause a much more abrupt muting of the output.
This abrupt muting is referred to as an analog mute and it will switch the analog outputs immediately
to VMID.
DE-EMPHASIS MODE
A digital de-emphasis filter may be applied to each DAC channel. The de-emphasis filter for each
stereo channel is enabled under the control of DEEMP[2:0]. DEEMP[0] enables the de-emphasis
filter for DAC 1, DEEMP[1] enables the de-emphasis filter for DAC 2, and DEEMP[2] enables the de-
emphasis filter for DAC 3.
REGISTER ADDRESS
R17
DAC Control 3
11h
BIT
LABEL
2:0 DEEMP[2:0]
4 DEEMPALL
DEFAULT
000
0
DESCRIPTION
De-emphasis mode select:
DEEMP[0] = 1, enable De-
emphasis on DAC1.
DEEMP[1] = 1, enable De-
emphasis on DAC2.
DEEMP[2] = 1, enable De-
emphasis on DAC3.
0 = De-emphasis controlled by
DEEMP[2:0]
1 = De-emphasis enabled on all
DACs
Table 27 De-emphasis Register
Refer to Figure 47, Figure 48, Figure 49 and Figure 50 for details of the De-Emphasis modes at
different sample rates.
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted
REGISTER ADDRESS BIT
R18
5:0
DAC Control 4
12h
LABEL
PHASE
[5:0]
DEFAULT
111111
DESCRIPTION
Controls phase of DAC outputs
0 = inverted
1 = non-inverted
PHASE[0] = 0 inverts phase of
DAC1L output
PHASE[1] = 0 inverts phase of
DAC1R output
PHASE[2] = 0 inverts phase of
DAC2L output
PHASE[3] = 0 inverts phase of
DAC2R output
PHASE[4] = 0 inverts phase of
DAC3L output
PHASE[5] = 0 inverts phase of
DAC3R output
Table 28 DAC Output Phase Register
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PD Rev 4.5 February 2008
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