WM8711_06 Datasheet, PDF (37/47 Pages) Wolfson Microelectronics plc – Internet Audio DAC with Integrated Headphone Amplifier

Production Data
WM8711 / WM8711L
REGISTER MAP
The complete register map is shown in Table 24. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER B B B B B B B B8
B7
B6
B5
B4
B3
B2
B1
B0
15 14 13 12 11 10 9
R2 (04h)
LRHP
0000010
LZCEN
BOTH
LHPVOL
R3 (06h)
RLHP
0000011
RZCEN
BOTH
RHPVOL
R4 (08h)
0000100
0
0
0
0 DAC SEL BYPASS 0
0
0
R5 (0Ah)
0000101
0
0
0
0
0 DAC MU
DEEMPH
0
POWER CLK
R6 (0Ch)
0000110
0
OSCPD OUTPD DACPD 1
1
1
OFF OUTPD
BCLK
R7 (0Eh)
0000111
0
MS LR SWAP LRP
IWL
INV
FORMAT
CLK0 CLKI
R8 (10h)
0001000
0
DIV2 DIV2
USB/
SR
BOSR
NORM
R9 (12h)
0001001
0
0
0
0
0
0
0
0
ACTIVE
R15(1Eh) 0 0 0 1 1 1 1
RESET
ADDRESS
DATA
Table 23 Mapping of Program Registers
REGISTER
ADDRESS
0000010
Left Headphone
Out
BIT
LABEL
6:0 LHPVOL
[6:0]
7
LZCEN
8
LRHPBOTH
DEFAULT
DESCRIPTION
1111001
( 0dB )
0
0
Left Channel Headphone Output
Volume Control
1111111 = +6dB
. . 1dB steps down to
0110000 = -73dB
0000000 to 0101111 = MUTE
Left Channel Zero Cross detect Enable
1 = Enable
0 = Disable
Left to Right Channel Headphone
Volume, Mute and Zero Cross Data
Load Control
1 = Enable Simultaneous Load of
LHPVOL[6:0] and LZCEN to
RHPVOL[6:0] and RZCEN
0 = Disable Simultaneous Load
w
PD Rev 4.3 September 2006
37