WM8731SED_13 Datasheet, PDF (36/65 Pages) Wolfson Microelectronics plc – Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

WM8731 / WM8731L
Production Data
DIGITAL AUDIO INTERFACES
WM8731/L may be operated in either one of the 4 offered audio interface modes. These are:
 Right justified
 Left justified
 I²S
 DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits.
Note that 32 bit data is not supported in right justified mode.
The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether
Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DACDAT is
always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in
master or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8731/L. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
1/fs
DACLRC/
ADCLRC
BCLK
LEFT CHANNEL
RIGHT CHANNEL
DACDAT/
ADCDAT
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 26 Left Justified Mode
I²S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or
ADCLRC transition.
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PD, Rev 4.9, October 2012
36