WM9090 Datasheet, PDF (35/81 Pages) Wolfson Microelectronics plc – Ultra Low Power Audio Subsystem

Production Data
WM9090
The sequence of signals associated with a single register write operation is illustrated in Figure 7.
Figure 7 Control Interface Register Write
The sequence of signals associated with a single register read operation is illustrated in Figure 8.
SCLK
SDA
D7
D1 R/W
A7
A1 A0
D6
D0 R/W
B15
B9 B8
B7
B1 B0
START
device ID (Write) ACK
register address
ACK
Rpt
START
device ID (Read) ACK
data bits B15 – B8
ACK
data bits B15 – B8
ACK
STOP
Note: The SDA pin is driven by both the master and slave devices in turn to transfer device address, register address, data and ACK responses
Figure 8 Control Interface Register Read
The Control Interface also supports other register operations, as listed above. The interface protocol
for these operations is summarised below. The terminology used in the following figures is detailed in
Table 18.
Note that multiple write and multiple read operations are supported using the auto-increment mode.
This feature enables the host processor to access sequential blocks of the data in the WM9090
register map faster than is possible with single register operations.
TERMINOLOGY
DESCRIPTION
S
Start Condition
Sr
Repeated start
A
Acknowledge (SDA Low)
¯A¯
Not Acknowledge (SDA High)
P
Stop Condition
R/¯W¯
ReadNotWrite
0 = Write
1 = Read
[White field]
Data flow from bus master to WM9090
[Grey field]
Data flow from WM9090 to bus master
Table 18 Control Interface Terminology
w
PD, November 2010, Rev 4.1
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